The present invention generally relates to the manufacture of semiconductor devices, and, more specifically, relates to the manufacture of semiconductor-on-insulator (SOI) tunneling junction transistor (TJT) static random access memory (SRAM) cell devices.
CMOS static random access memories (SRAM) are used in the semiconductor and computer industries because of the combination of speed, low power, and no requirement for refresh. Information can be written into and read out of an SRAM cell faster than with a DRAM cell, because the transistors of the SRAM cell can be switched faster than capacitors can be charged and drained. However, one disadvantage of prior art SRAM cells is that such cells have required a larger footprint to achieve greater speed and stability than DRAM cells.
One technique attempted to overcome this disadvantage by stacking MOS transistors in a vertical arrangement. Typically, a driver transistor is formed in the substrate having source, drain, and channel regions in the substrate and a gate electrode overlaying the substrate surface. Then, a load transistor is formed in a thin-film layer overlying the first transistor. By adding an additional electrical component to the device, the thin-film transistor increases the functional capacity of a device while not consuming additional surface area, or requiring further downsizing of components.
While stacking transistors in a vertical arrangement reduces the surface area of a memory cell, valuable surface area must still be allocated for coupling electrical signals to the memory cell. Metal leads overlying the cell typically introduce the electrical signals. As the overall area dimensions of the cell decrease, the metal leads carrying electrical signals to and from the cell must be brought closer together. Constructing a memory cell with stacked transistors can aggravate this problem because elaborate contact interconnection schemes are typically required in a stacked transistor memory cell.
Additionally, such stacked cells suffer from high off-state current requirements due to the lack of isolation provided by channel side barriers (CSB). Further, typical barriers used in the source and drain regions to adjust the source impedance to the CSB fail to act as diffusion barriers, thus allowing the impurity level within the channel to increase, and requires a higher leakage current such as the gate induced drain leakage current at the drain side.
Therefore, there exists a need in the art for an SOI SRAM transistor device with increased performance, reduced layout area and better characteristics enhanced by barriers, particularly for an SOI transistor SRAM cell device.
According to one aspect of the invention, the invention is a tunneling junction transistor (TJT) SRAM cell device formed on a semiconductor-on-insulator (SOI) substrate. The SOI TJT SRAM cell device includes a first gate defining a channel (a p-type doped region) interposed between a source and a drain formed within one of the active regions defined by isolation trenches of the SOI substrate. A second gate has a thin nitride layer interposed between an undoped region and a first gate electrode, a side gate electrode, and a polysilicon layer. A contact plug is adjacent and in electrical contact with at least one of the source and the drain. The SOI TJT SRAM cell device has at least one of a plurality of electrical connections electrically coupled respectively to at least one node.
According to another aspect of the invention, the invention is a method of fabricating an SOI TJT SRAM cell device. The method includes the step of forming within an active region of an SOI substrate a source and a drain with a p-type region interposed between. The method further includes the step of forming a first gate on the active region and forming a second gate on the first gate. Additionally, the method includes the step of forming a contact plug adjacent to the stacked first and second gates and in electrical contact with the source. The contact plug electrically couples one of the active regions to a node.
According to another aspect of the invention, the invention is an SOI TJT SRAM cell device. The SOI TJT SRAM cell device includes a first gate defining a channel (a p-type doped region) interposed between a source and a drain formed within an active region defined by isolation trenches of the SOI substrate. A second gate has a thin nitride layer interposed between an undoped region and a first gate electrode, a side gate electrode, and a polysilicon layer. A first contact plug is adjacent and in electrical contact with at least one of the source and the drain. A second contact plug is adjacent and in electrical contact with the side gate electrode of the second gate. The SOI TJT SRAM cell device has at least one of a plurality of electrical connections electrically coupled respectively to at least one node.